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TDF8599B
I2C-bus controlled dual channel 43 W/4 , single channel 85 W/1 class-D power amplifier with load diagnostics
Rev. 01 -- 29 July 2009 Product data sheet
1. General description
The TDF8599B is a dual Bridge-Tied Load (BTL) car audio amplifier comprising an NDMOST-NDMOST output stage based on SOI BCDMOS technology. Low power dissipation enables the TDF8599B high-efficiency, class-D amplifier to be used with a smaller heat sink than those normally used with standard class-AB amplifiers. The TDF8599B can operate in either non-I2C-bus mode or I2C-bus mode. When in I2C-bus mode, DC load detection results and fault conditions can be easily read back from the device. Up to 15 I2C-bus addresses can be selected depending on the value of the external resistor connected to pins ADS and MOD. When pin ADS is short circuited to ground, the TDF8599B operates in non-I2C-bus mode. Switching between Operating mode and Mute mode in non-I2C-bus mode is only possible using pins EN and SEL_MUTE.
2. Features
I I I I I I I I I I I I I I I High-efficiency Low quiescent current Operating voltage from 8 V to 24 V Two 4 /2 capable BTL channels or one 1 capable BTL channel Differential inputs I2C-bus mode with 15 I2C-bus addresses or non-I2C-bus mode operation Clip detect Independent short circuit protection for each channel Advanced short circuit protection for load, GND and supply Load dump protection Thermal foldback and thermal protection DC offset protection Selectable AD or BD modulation Parallel channel mode for high current drive capability Advanced clocking: N Switchable oscillator clock source: internal for Master mode or external for Slave mode N Spread spectrum mode N Phase staggering N Frequency hopping I No `pop noise' caused by DC output offset voltage
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
I I2C-bus mode: N DC load detection N AC load detection N Thermal pre-warning diagnostic level setting N Identification of activated protections or warnings N Selectable diagnostic information available using pins DIAG and CLIP I Qualified in accordance with AEC-Q100
3. Applications
I Car audio
4. Quick reference data
Table 1. Quick reference data VP = 14.4 V unless otherwise stated. Symbol VP IP Iq(tot) Po Parameter supply voltage supply current total quiescent current output power off state; Tj 85 C; VP = 14.4 V Operating mode; no load, snubbers and filter connected Stereo mode: VP = 14.4 V; THD = 1 %; RL = 4 VP = 14.4 V; THD = 10 %; RL = 4 square wave (EIAJ); RL = 4 VP = 24 V; THD = 10 %; RL = 4 VP = 14.4 V; THD = 1 %; RL = 2 VP = 14.4 V; THD = 10 %; RL = 2 square wave (EIAJ); RL = 2 Parallel mode: VP = 14.4 V; THD = 10 %; RL = 1 VP = 24 V; THD = 10 %; RL = 2 VP = 24 V; THD = 1 %; RL = 1
[1] [2] In this data sheet supply voltage VP describes VP1, VP2 and VPA. Output power is measured indirectly based on RDSon measurement.
[2] [2]
Conditions
[1]
Min 8 -
Typ 14.4 2 90
Max 24 10 120
Unit V A mA
18 24 29 39 135
20 26 40 70 32 43 70 85 138 150
-
W W W W W W W W W W
5. Ordering information
Table 2. Ordering information Package Name TDF8599BTH HSOP36 Description plastic, heatsink small outline package; 36 leads; low stand-off height Version SOT851-2 Type number
TDF8599B_1
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
6. Block diagram
VDDA 10 9 8 DRIVER HIGH PWM CONTROL IN1P 1 DRIVER LOW PGND1 VP1 IN1N 2 PWM CONTROL DRIVER LOW ACGND 5
+
VP1 31
VP2 24
AGND SVRR
STABI1
34 32 VP1
VSTAB1 BOOT1N
TDF8599B
33
OUT1N
29
BOOT1P
DRIVER HIGH 28 OUT1P
PGND1 VP2 DRIVER HIGH PWM CONTROL
23
BOOT2N
22 DRIVER LOW PGND2 VP2 26
OUT2N
IN2P
3
BOOT2P
IN2N
4 PWM CONTROL
DRIVER HIGH 27 DRIVER LOW OUT2P
OSCSET OSCIO SSM MOD VDDD EN SEL_MUTE SCL SDA ADS
18 19 17 12 35 6 7 16 15 11 36 GNDD/HW 14 DIAG 13 20 MODE SELECT + I2C-BUS DIAGNOSTICS OSCILLATOR
PGND2
5 V STABI
STABI2
21
VSTAB2
PROTECTION OVP, OCP, OTP UVP, TFP, WP, DCP 30 PGND1 25 PGND2
001aak214
CLIP DCP
Fig 1.
Block diagram
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
7. Pinning information
7.1 Pinning
GNDD/HW 36 VDDD 35 VSTAB1 34 OUT1N 33 BOOT1N 32 VP1 31 PGND1 30 BOOT1P 29 OUT1P 28 OUT2P 27 BOOT2P 26 PGND2 25 VP2 24 BOOT2N 23 OUT2N 22 VSTAB2 21 DCP 20 OSCIO 19
001aak215
1 2 3 4 5 6 7 8
IN1P IN1N IN2P IN2N ACGND EN SEL_MUTE SVRR AGND
TDF8599BTH
9
10 VDDA 11 ADS 12 MOD 13 CLIP 14 DIAG 15 SDA 16 SCL 17 SSM 18 OSCSET
Fig 2.
Heatsink up (top view) pin configuration TDF8599BTH
7.2 Pin description
Table 3. Symbol IN1P IN1N IN2P IN2N ACGND EN Pin description Pin 1 2 3 4 5 6 Type[1] I I I I I I Description channel 1 positive audio input channel 1 negative audio input channel 2 positive audio input channel 2 negative audio input decoupling for input reference voltage enable input: non-I2C-bus mode: switch between off and Mute mode I2C-bus mode: off and Standby mode SEL_MUTE SVRR AGND VDDA ADS MOD
TDF8599B_1
7 8 9 10 11 12
I I G P I I
select mute or unmute decoupling for internal half supply reference voltage analog supply ground analog supply voltage non-I2C-bus mode: connected to ground I2C-bus mode: selection and address selection pin modulation mode, phase shift and parallel mode select
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Pin description ...continued Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 G O G P O O P G O I/O I Type[1] O O I/O I Description clip output; open-drain diagnostic output; open-drain I2C-bus data input and output I2C-bus clock input master setting: Spread spectrum mode frequency slave setting: phase lock operation master/slave oscillator setting master only setting: set internal oscillator frequency external oscillator slave setting: input internal oscillator master setting: output DC protection input for the filtered output voltages decoupling internal stabilizer 2 for DMOST drivers channel 2 negative PWM output boot 2 negative bootstrap capacitor channel 2 power supply voltage channel 2 power ground boot 2 positive bootstrap capacitor channel 2 positive PWM output channel 1 positive PWM output boot 1 positive bootstrap capacitor channel 1 power ground channel 1 power supply voltage boot 1 negative bootstrap capacitor channel 1 negative PWM output decoupling internal stabilizer 1 for DMOST drivers decoupling of the internal 5 V logic supply ground digital supply voltage handle wafer connection
Table 3. Symbol CLIP DIAG SDA SCL SSM OSCSET OSCIO DCP VSTAB2 OUT2N BOOT2N VP2
[2]
PGND2 BOOT2P OUT2P OUT1P BOOT1P PGND1 VP1[2] BOOT1N OUT1N VSTAB1 VDDD GNDD/HW
[1] [2]
I = input, O = output, I/O = input/output, G = ground and P = power supply. In this data sheet supply voltage VP describes VP1, VP2 and VPA.
8. Functional description
8.1 General
The TDF8599B is a dual full bridge (BTL) audio power amplifier using class-D technology. The audio input signal is converted into a Pulse-Width Modulated (PWM) signal using the analog input and PWM control stages. A PWM signal is applied to driver circuits for both high-side and low-side enabling the DMOS power output transistors to be driven. An external 2nd order low-pass filter converts the PWM signal into an analog audio signal across the loudspeakers.
TDF8599B_1
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
The TDF8599B includes integrated common circuits for all channels such as the oscillator, all reference sources, mode functionality and a digital timing manager. In addition, the built-in protection includes thermal foldback, temperature, overcurrent and overvoltage (load dump). The TDF8599B operates in either I2C-bus mode or non-I2C-bus mode. In I2C-bus mode, DC load detection, frequency hopping and extended configuration functions are provided together with enhanced diagnostic information.
8.2 Mode selection
The mode pins EN, ADS and SEL_MUTE enable mute state, I2C-bus mode and Operating mode switching. Pin SEL_MUTE is used to mute and unmute the device and must be connected to an external capacitor (CON). This capacitor generates a time constant which is used to ensure smooth fade-in and fade-out of the input signal. The TDF8599B is enabled when pin EN is HIGH. When pin EN is LOW, the TDF8599B is off and the supply current is at its lowest value (typically 2 A). When off, the TDF8599B is completely deactivated and will not react to I2C-bus commands. I2C-bus mode is selected by connecting a resistor between pins ADS and AGND. In I2C-bus mode with pin EN HIGH, the TDF8599B waits for further commands (see Table 4). I2C-bus mode is described in Section 9 on page 23. Non-I2C-bus mode is selected by connecting pin ADS to pin AGND. In non-I2C-bus mode, the default TDF8599B state is Mute mode. The amplifiers switch idle (50 % duty cycle) and the audio signal is suppressed at the output. In addition, the capacitor (CSVRR) is charged to half the supply voltage. To enter Operating mode, pin SEL_MUTE must be HIGH with S1 open, enabling capacitor (CON) charged by an internal pull-up (see Figure 3). In addition, pin EN must be driven HIGH.
S2
3.3 V
EN
S2
3.3 V
EN
TDF8599B
SEL_MUTE AGND
CON S1
ADS SEL_MUTE
TDF8599B
ADS
RADS
AGND
CON
001aak216
001aak217
a. Non-I2C-bus mode
b. I2C-bus mode
See Table 13 for detailed information on RADS.
Fig 3.
Mode selection
I2C-bus mode and non-I2C-bus mode control are described in Table 4 on page 7 and Table 5 on page 7. Switches S1 and S2 are shown in Figure 3.
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
I2C-bus mode operation Pin SEL_MUTE HIGH LOW LOW Bit IB1[D0] 1 1 0 X[1] Bit IB2[D0] 0 1 X[1] X[1] Mode Operating mode Mute mode Standby mode off (default)
Table 4. Pin EN
HIGH (S2 closed)
LOW (S2 open)
[1] X = do not care.
X[1]
Table 5. Pin EN
Non-I2C-bus mode operation Pin SEL_MUTE HIGH (S1 open) LOW (S1 closed) X[1] Mode Operating mode Mute mode (default) off
HIGH (S2 closed) LOW (S2 open)
[1] X = do not care.
8.3 Pulse-width modulation frequency
The output signal from the amplifier is a PWM signal with a clock frequency of fosc. This frequency is set by connecting a resistor (Rosc) between pins OSCSET and AGND. The optimal clock frequency setting is between 300 kHz and 400 kHz. Connecting a resistor with a value of 39 k, for example, sets the clock frequency to 320 kHz (see Figure 5). The external capacitor (Cosc) has no influence on the oscillator frequency. It does however, reduce jitter and sensitivity to disturbance. Using a 2nd order LC demodulation filter in the application generates an analog audio signal across the loudspeaker.
8.3.1 Master and slave mode selection
In a master and slave configuration, multiple TDF8599B devices are daisy-chained together in one audio application with a single device providing the clock frequency signal for all other devices. In this situation, it is recommended that the oscillators of all devices are synchronized for optimum EMI behavior as follows: All OSCIO pins are connected together and one TDF8599B in the application is configured as the clock-master. All other TDF8599B devices are configured as clock-slaves (see Figure 5).
* The clock-master pin OSCIO is configured as the oscillator output. When a resistor
(Rosc) is connected between pins OSCSET and AGND, the TDF8599B is in Master mode.
* The clock-slave pins OSCIO are configured as the oscillator inputs. When pin
OSCSET is directly connected to pin AGND (see Table 6), the TDF8599B is in Slave mode.
Table 6. Mode Master Slave Mode setting pin OSCIO Settings Pin OSCSET Rosc > 26 k Rosc = 0 ; shorted to pin AGND Pin OSCIO output input
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
The value of the resistor Rosc sets the clock frequency based on Equation 1: 12.45 x 10 f osc = --------------------------- [ Hz ] R osc
9
(1)
50 Rosc (k) 40
001aak224
30
20
10
0 300
350
400
450 500 fosc (kHz)
Fig 4.
Clock frequency as a function of Rosc
OSCSET
OSCSET
Rosc Cosc
OSCSET
TDF8599B
OSCIO Master
TDF8599B
OSCIO
TDF8599B
OSCIO Slave 2
001aak218
fosc
R
Slave 1
Fig 5.
Master and slave configuration
In Master mode, Spread spectrum mode and frequency hopping can be enabled. In Slave mode, phase staggering and phase lock operation can be selected. An external clock can be used as the master-clock on pin OSCIO of the slave devices. When using an external clock, it must remain active during the shutdown sequence to ensure that all devices are switched off and able to enter the off state as described in Section 8.2 on page 6. In Slave mode, an internal watchdog timer on pin OSCIO is triggered when the TDF8599B is switched off by pulling down pin EN. If the external clock fails, the watchdog timer forces the TDF8599B to switch off.
8.3.2 Spread spectrum mode (Master mode)
Spread spectrum mode is a technique of modulating the oscillator frequency with a slowly varying signal to broaden the switching spectrum, thereby reducing the spectral density of the EMI. Connecting a capacitor (CSSM) to pin SSM enables Spread spectrum mode (see Figure 6). When pin SSM is connected to pin AGND, Spread spectrum mode is disabled.
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
The capacitor on pin SSM (CSSM) sets the spreading frequency when Spread spectrum mode is active. The current (ISSM) flowing in and out of pin SSM is typically 5 A. This gives a triangular voltage on pin SSM that sweeps around the voltage set by pin OSCSET 5 %. The voltage on pin SSM is used to modulate the oscillator frequency. The spread spectrum frequency (fSSM) can be calculated using Equation 2: I SSM f SSM = ----------------------------------------------------- [ Hz ] 2 x C SSM x V 1 x 10 % where the voltage on pin OSCSET = V1 and is calculated as 100 A x Rosc (V) with ISSM = 5 A. (2)
100 A
100 A
OSCSET
Rosc Cosc 5 A ISSM
OSCSET
Rosc Cosc
SSM
SSM
CSSM
001aai773
001aai774
a. Off Fig 6. Spread spectrum mode
b. On
The frequency swings between 0.95 x fosc and 1.05 x fosc; see Figure 7.
OSCIO
max(V)
SSM
min(V) t (ms)
001aai775
Fig 7.
Spread spectrum operation in Master mode
8.3.3 Frequency hopping (Master mode)
Frequency hopping is a technique used to change the oscillator frequency for AM tuner compatibility. In Master mode, the resistor connected between pins OSCSET and AGND sets the oscillator frequency (fosc). In I2C-bus mode, this frequency can be varied by 10 %. Set bit IB1[D4] to logic 1 and bit IB1[D3] to either logic 0 (0.9 x fosc) or logic 1 (1.1 x fosc).
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Product data sheet
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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect of the external oscillator signal connected to pin OSCIO. Phase lock operation is also needed to enable phase staggering, see Section 8.4.2 on page 13. Phase lock operation is enabled when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and CPLL_p) and a resistor (RPLL) between pin SSM and pin AGND (see Figure 8). Connecting pin SSM to pin AGND disables phase lock operation and causes the slave to directly use the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on the desired loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL = 8.4 x BPLL . The corresponding values for CPLL_s and CPLL_p are given by Equation 3 and Equation 4: 0.032 C PLL_p = ------------------------------ [ F ] R PLL x B PLL (3)
Remark: CPLL_p is only needed when 14 phase shift is selected. See Section 8.4.2 for more detailed information. 0.8 C PLL_s = ------------------------------ [ F ] R PLL x B PLL (4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled, the PLL loop bandwidth BPLL should be 100 x fSSM.
100 A
OSCSET
100 A
OSCSET SSM
CPLL_s RPLL CPLL_p(1)
PLL SSM
PLL
001aai776
001aai777
(1) Only needed when 14 phase shift is selected.
a. Off Fig 8. Phase lock operation
b. On
Table 7 lists all oscillator modes.
Table 7. Oscillator modes OSCIO pin output output input input SSM pin CSSM to pin AGND shorted to pin AGND CPLL + RPLL to pin AGND shorted to pin AGND Oscillator modes master, spread spectrum master, no spread spectrum slave, PLL enabled slave, PLL disabled
OSCSET pin Rosc > 26 k Rosc > 26 k Rosc = 0 Rosc = 0
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
8.4 Operation mode selection
Pin MOD is used to select specific operating modes. The resistor (RMOD) connected between pins MOD and AGND together with the non-I2C-bus/I2C-bus mode determine the operating mode (see Table 8). The mode of operation depends on whether non-I2C-bus mode or I2C-bus mode is active. This in turn is determined by the resistor value connected between pins ADS and AGND. In non-I2C-bus mode, pin MOD is used to select:
* AD or BD modulation (see Section 8.4.1). * 12 phase shift when oscillator is used in Slave mode (see Section 8.4.2). * Parallel mode operation (see Section 8.4.3).
In I2C-bus mode, pin MOD can only select Parallel mode. In addition, the modulation mode and phase shift are programmed using I2C-bus commands.
Table 8. RMOD (k) 4.7 13 33 100 (open)
[1] [2] [3] RADS 4.7 k; See Table 13 on page 23. RADS = 0 ; pin ADS is short circuited to pin AGND. See Section 8.4.3 on page 14 for more detailed information.
Operation mode selection with the MOD pin I2C-bus mode[1] Non-I2C-bus mode[2] AD modulation: no phase shift in Slave mode BD modulation: no phase shift in Slave mode AD modulation: 12 phase shift in Slave mode Parallel mode[3] BD modulation: 12 phase shift in Slave mode AD modulation: no phase shift in Slave mode BD modulation: no phase shift in Slave mode
0 (short to AGND) Stereo mode
In I2C-bus mode, pin MOD is latched using the I2C-bus command IB3[D7] = 1. This avoids amplifier switching interference generating incorrect information on pin MOD. In non-I2C-bus mode or when IB3[D7] = 0, the information on pin MOD is latched when one of the TDF8599B's outputs starts switching.
8.4.1 Modulation mode
In non-I2C-bus mode, pin MOD is used to select either AD or BD modulation mode (see Table 8). In I2C-bus mode, the modulation mode is selected using an I2C-bus command.
* AD modulation mode: the bridge halves switch in opposite phase. * BD modulation mode: the bridge halves switch in phase but the input signal for the
modulators is inverted. Figure 10 and Figure 11 show simplified representations of AD and BD modulation.
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Product data sheet
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
+VP INxP
+VP INxN
OUTP OUTN
AD BD
001aai778
Fig 9.
AD/BD modulation switching circuit
INxP
OUTxP
001aai779
a. Bridge half 1.
INxN
OUTxN
001aai780
b. Bridge half 2 switched in the opposite phase to bridge half 1. Fig 10. AD modulation
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
INxP
OUTxP
OUTxP, OUTxN
001aai781
a. Phase switching cycle.
INxN
OUTxN
001aai782
b. Inverted signal to the modulator. Fig 11. BD modulation
8.4.2 Phase staggering (Slave mode)
In Slave mode with phase lock operation enabled, a phase shift with respect to the incoming clock signal can be selected to distribute the switching moments over time. In non-I2C-bus mode, 12 phase shift can be programmed using pin MOD. In I2C-bus mode, five different phase shifts (14 , 13 , 12 , 23 , 34 ) can be selected using the I2C-bus bits (IB3[D1:D3]). See Table 8 for selection of the phase shift in non-I2C-bus mode with pin MOD. An additional capacitor must be connected to pin SSM when 14 phase shift is used (see Figure 8). An example of using 12 phase shift for BD modulation is shown in Figure 12.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
OUT1P
phase 0
OUT1N master OUT2P
OUT2N
OUT1P 1 2 OUT1N slave OUT2P 2 3
001aai783
OUT2N
Fig 12. Master and slave operation with 12 phase shift
8.4.3 Parallel mode
In Parallel mode; the two output stages operate in parallel to enlarge the drive capability. The inputs and outputs for Parallel mode must be connected on the Printed-Circuit Board (PCB) as shown in Figure 13. The parallel connection can be made after the output filter, as shown in Figure 13 or directly to the device output pins (OUTxP and OUTxN).
+ -
IN1P
OUT1N -
IN1N
OUT1P
IN2N
TDF8599B
OUT2P +
IN2P
MOD
RMOD
OUT2N
001aak219
Fig 13. Parallel mode
In Parallel mode, the channel 1 I2C-bus bits can be programmed using the I2C-bus.
8.5 Protection
The TDF8599B includes a range of built-in protection functions. How the TDF8599B manages the various possible fault conditions for each protection is described in the following sections:
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Overview of protection types Reference Section 8.5.1 Section 8.5.2 Section 8.5.3 Section 8.5.4 Section 8.5.5 Section 8.5.6 Section 8.5.6
Table 9.
Protection type Thermal foldback Overtemperature Overcurrent Window DC Offset Undervoltage Overvoltage
8.5.1 Thermal foldback
Thermal Foldback Protection (TFP) is activated when the average junction temperature exceeds the threshold level (145 C). TFP decreases amplifier gain such that the combination of power dissipation and Rth(j-a) create a junction temperature around the threshold level. The device will not completely switch off but remains operational at the lower output power levels. If the average junction temperature continues to increase, a second built-in temperature protection threshold level shuts down the amplifier completely.
8.5.2 Overtemperature protection
If the average junction temperature (Tj) > 160 C, OverTemperature Protection (OTP) is activated and the power stage shuts down immediately.
8.5.3 Overcurrent protection
OverCurrent Protection (OCP) is activated when the output current exceeds the maximum output current of 8 A. OCP regulates the output voltage such that the maximum output current is limited to 8 A. The amplifier outputs keep switching and the amplifier is NOT shutdown completely. This is called current limiting. OCP also detects when the loudspeaker terminals are short circuited or one of the amplifier's demodulated outputs is short circuited to one of the supply lines. In either case, the shorted channel(s) are switched off. The amplifier can distinguish between loudspeaker impedance drops and a low-ohmic short across the load or one of the supply lines. This impedance threshold depends on the supply voltage used. When a short is made across the load causing the impedance to drop below the threshold level, the shorted channel(s) are switched off. They try to restart every 50 ms. If the short circuit condition is still present after 50 ms, the cycle repeats. The average power dissipation will be low because of this reduced duty cycle. When a channel is switched off due to a short circuit on one of the supply lines, Window Protection (WP) is activated. WP ensures the amplifier does not start-up after 50 ms until the supply line short circuit is removed.
8.5.4 Window protection
Window Protection (WP) checks the PWM output voltage before switching from Standby mode to Mute mode (with both outputs switching) and is activated as follows:
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I2C-bus controlled dual channel class-D power amplifier
* During the start-up sequence:
- When the TDF8599B is switched from standby to mute (td(stb-mute)). When a short circuit on one of the output terminals (i.e. between VP or GND) is detected, the start-up procedure is interrupted and the TDF8599B waits for open circuit outputs. No large currents flow in the event of a short circuit to the supply lines because the check is performed before the power stages are enabled.
* During operation:
- A short to one of the supply lines activates OCP causing the amplifier channel to shutdown. After 50 ms the amplifier channel restarts and WP is activated. However, the corresponding amplifier channel will not start-up until the supply line short circuit has been removed.
8.5.5 DC offset protection
DC offset Protection (DCP) is activated when the DC content in the demodulated output voltage exceeds a set threshold (typically 2 V). DCP is active in both Mute mode and Operating mode. Figure 14 shows how false triggering of the DCP by low frequencies in the audio signal is prevented using the external capacitor (CF) to generate a cut-off frequency.
OUT1P
OUT1N OUT2P
OUT2N V to I
IB1[D6]
V to I
IB2[D6]
Vref
50 k
DCP
CF
DIAG
IB1[D7] DB1[D2] S4 IB2[D7] S3
S
Q
switch off channels
001aak078
Fig 14. DC offset protection and diagnostic output
In I2C-bus mode, DC offsets generate a voltage shift around the bias voltage. When the voltage shift exceeds threshold values, the offset alarm bit DB1[D2] is set and if bit IB1[D7] is not set, diagnostic information is also given. Any detected offset shuts down both channels when bit IB2[D7] is not set. To restart the TDF8599B in I2C-bus mode, pin EN must be toggled or DCP disabled by connecting pin DCP to pin AGND.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
In non-I2C-bus mode, when an offset is detected, DCP always gives diagnostic information on pin DIAG and shuts down both channels. Connecting a capacitor between pins DCP and AGND enables DC offset protection. Connecting pin DCP to pin AGND disables DCP in both I2C-bus and non-I2C-bus mode.
8.5.6 Supply voltages
UnderVoltage Protection (UVP) is activated when the supply voltage drops below the UVP threshold. UVP triggers the UVP circuit causing the system to first mute and then stop switching. When the supply voltage rises above the threshold level, the system restarts. OverVoltage Protection (OVP) is activated when the supply voltage exceeds the OVP threshold. The OVP (or load dump) circuit is activated and the power stages are shutdown. An overview of all protection circuits and the amplifier states is given in Table 10.
8.5.7 Overview of protection circuits and amplifier states
Table 10. Overview of TDF8599B protection circuits and amplifier states Amplifier state Complete shutdown TFP OTP OCP WP DCP UVP OVP
[1] [2] [3] [4] [5] [6] When fault is removed. Amplifier gain depends on the junction temperature and size of the heat sink. TFP influences restart timing depending on heat sink size. Shorted load causes a restart of the channel every 50 ms. Latched protection is reset by toggling pin EN or by disabling DCP in I2C-bus mode. In I2C-bus mode deep supply voltage drops will cause a Power-On Reset (POR). The restart requires an I2C-bus command.
Protection circuit name
Channel shutdown N[2] N Y Y N N N
Restart[1] Y[3] Y[3] Y[4] Y N[5] Y[6] Y
N[2] Y N N Y Y Y
8.6 Diagnostic output
8.6.1 Diagnostic table
The diagnostic information for I2C-bus mode and non-I2C-bus mode is shown in Table 11. The instruction bitmap and data bytes are described in Table 14 and Table 15. Pins DIAG and CLIP have an open-drain output which must have an external pull-up resistor connected to an external voltage. Pins CLIP and DIAG can show both fixed and I2C-bus selectable information.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Pin DIAG goes LOW when a short circuit to one of the amplifier outputs occurs. The microprocessor reads the failure information using the I2C-bus. The I2C-bus bits are set for a short circuit. These bits can be reset with the I2C-bus read command. Even after the short has been removed, the microprocessor knows what was wrong after reading the I2C-bus. Old information is read when a single I2C-bus read command is used. To read the current information, two read commands must be sent, one after another. When selected, pin DIAG gives the current diagnostic information. Pin DIAG is released instantly when the failure is removed, independent of the I2C-bus latches.
Table 11. Diagnostic Power-on reset UVP or OVP Clip detection Temperature pre-warning OCP/WP DCP OTP Available data on pins DIAG and CLIP I2C-bus mode Pin DIAG yes yes no no yes selectable yes Pin CLIP yes no selectable selectable no no no Non-I2C-bus mode Pin DIAG yes yes no no yes yes yes Pin CLIP yes no yes yes no no no
When OCP is triggered, the open-drain DIAG output is activated. The diagnostic output signal during different short circuit conditions is illustrated in Figure 15.
shorted load AMPLIFIER RESTART
short to GND or VP line NO RESTART
pull up V
AGND = 0 V 50 ms 50 ms 50 ms
001aai786
Fig 15. Diagnostic output for short circuit conditions
8.6.2 Load identification (I2C-bus mode only)
8.6.2.1 DC load detection DC load detection is only available in I2C-bus mode and is controlled using bit IB2[D2]. The default setting is logic 0 for bit IB2[D2] which disables DC load detection. DC load detection is enabled when bit IB2[D2] = 1. Load detection takes place before the class-D amplifier output stage starts switching in Mute mode and the start-up time from Standby mode to Mute mode is increased by tdet(DCload) (see Figure 16).
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
VP DRIVER HIGH PWM CONTROL DRIVER LOW
B
OUTN
PGND1
RL
VP DRIVER HIGH PWM CONTROL DRIVER LOW OUTP
PGND2
001aai787
Fig 16. DC load detection circuit
out (V)
out- out+ t (s) td(stb-mute) tdet(DCload)
001aai788
Fig 17. DC load detection procedure
The capacitor connected to pin SEL_MUTE (see Figure 3 on page 6) is used to create an inaudible current test pulse, drawn from the positive amplifier output. The diagnostic `speaker load' (or `open load'), based on the voltage difference between pins OUTxP and OUTxN is shown in Figure 18.
SPEAKER LOAD 0 25 350
OPEN LOAD
001aaj956
Fig 18. DC load detection limits
Remark: DC load detection identifies a short circuited speaker as a valid speaker load. OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2, performs diagnostics on shorted loads. However, the diagnostics are performed after the DC load detection cycle has finished and once the amplifier is in Operating mode. The result of the DC load detection is stored in bits DB1[D4] and DB2[D4].
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I2C-bus controlled dual channel class-D power amplifier
Interpretation of DC load detection bits OCP bits DB1[D3] and DB2[D3] 0 1 0 Description speaker load shorted load open load
Table 12. 0 0 1
DC load bits DB1[D4] and DB2[D4]
Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load detection is interrupted by a sudden large change in supply voltage (triggered by UVP or OVP) or if the amplifier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC load detection enable bit IB2[D2] must be reset after the DC load protection cycle to release any amplifier hang-up. Once the DC load detection cycle has finished, DC load detection can be restarted by toggling the DC load detection enable bit IB2[D2]. However, this can only be used if both amplifier channels have not been enabled with bit IB1[D1] or bit IB2[D1]. See Section 8.6.2.2 "Recommended start-up sequence with DC load detection enabled" for detailed information. 8.6.2.2 Recommended start-up sequence with DC load detection enabled The flow diagram (Figure 19) illustrates the TDF8599B's ability to perform a DC load detection without starting the amplifiers. After a DC load detection cycle finishes without setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is toggled). To limit the maximum number of DC load detection cycle loops, a counter and limit have been added. The loop exits after the predefined number of cycles (COUNTMAX), if the DC load detection cycle finishes with an invalid detection. Depending on the application needs, the invalid DC load detection cycle can be handled as follows:
* the amplifier can be started without DC load detection * the DC load detection loop can be executed again
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
IB1[D0] = 1 IB2[D2] = 1 IB1[D1] = 1 IB2[D1] = 1
I2C-bus TX startup enable DC load disable channel 1 disable channel 2
COUNT = 0
WAIT DC load
IB1[D0] = 1 IB2[D2] = 1 IB1[D1] = 1 IB2[D1] = 1
I2C-bus TX startup enable DC load disable channel 1 disable channel 2 NO restart DC load
DB1[D4] = 1 DB2[D4] = 1 DB1[D6] = 1
I2C-bus RX channel 1 open load channel 2 open load DC load valid
COUNT COUNTMAX
YES
ERROR HANDLING
COUNT = COUNT + 1 IB1[D0] = 1 IB2[D2] = 0 IB1[D1] = 1 IB2[D1] = 1 DB1[D6] = 1 DC load valid NO
I2C-bus TX startup disable DC load disable channel 1 disable channel 2
start amplifier anyway
YES I2C-bus TX startup disable DC load enable channel 1 enable channel 2
001aaj061
IB1[D0] = 1 IB2[D2] = 0 IB1[D1] = 0 IB2[D1] = 0
Fig 19. Recommended start-up sequence with DC load detection enabled
8.6.2.3
AC load detection AC load detection is only available in I2C-bus mode and is controlled using bit IB3[D4]. The default setting for bit IB3[D4] = 0 disables AC load detection. When AC load detection is enabled (bit IB3[D4] = 1), the amplifier load current is measured and compared with a reference level. Pin CLIP is activated when this threshold is reached. Using this information, AC load detection can be performed using a predetermined input signal frequency and level. The frequency and signal level should be chosen so that the load current exceeds the programmed current threshold when the AC coupled load (tweeter) is present.
8.6.2.4
CLIP detection CLIP detection gives information for clip levels 0.2 %. Pin CLIP is used as the output for the clip detection circuitry on both channel 1 and channel 2. Setting either bit IB1[D5] or bit IB2[D5] to logic 0 defines which channel reports clip information on the CLIP pin.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
8.6.3 Start-up and shutdown sequence
To prevent switch on or switch off `pop noise', a capacitor (CSVRR) connected to pin SVRR is used to smooth start-up and shutdown. During start-up and shutdown, the output voltage tracks the voltage on pin SVRR. Increasing CSVRR results in a longer start-up and shutdown time. Enhanced pop noise performance is achieved by muting the amplifier until the SVRR voltage reaches its final value and the outputs start switching. The value of capacitor connected to pin SEL_MUTE (CON) determines the unmute and mute timing. The voltage on pin SEL_MUTE determines the amplifier gain. Increasing CON increases the unmute and mute times. In addition, a larger CON value increases the DC load detection cycle. When the amplifier is switched off with an I2C-bus command or by pulling pin EN LOW, the amplifier is first muted and then capacitor (CSVRR) is discharged. In Slave mode, the device enters the off state immediately after capacitor (CSVRR) is discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of approximately 50 ms to allow slave devices to enter the off state. When an external clock is connected to pin OSCIO (in Slave mode), the clock must remain active during the shutdown sequence for delay (td(1)) to ensure that the slaved TDF8599B devices are able to enter the off state.
VDDA
DIAG td(1) EN
ACGND td(3) IB1[D0] and IB2[D0] = 0 td(mute-fgain)
mute delay td(2)
SEL_MUTE
SVRR twake OUTn td(stb-mute) tdet(DCload)
001aai790
(1) Shutdown hold delay. (2) Master mode shutdown delay. (3) Shutdown delay.
Fig 20. Start-up and shutdown timing in I2C-bus mode with DC load detection
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
VDDA
DIAG td(2) EN td(1)
ACGND td(mute-fgain) SEL_MUTE td(3)
SVRR
td(stb-mute) OUTn
001aai791
(1) Shutdown hold delay. (2) Shutdown delay. (3) Master mode shutdown delay.
Fig 21. Start-up and shutdown timing in non-I2C-bus mode
9. I2C-bus specification
TDF8599B address with hardware address select.
Table 13. I2C-bus write address selection using pins MOD and ADS RMOD[1] (k) Stereo mode 0[2] Open 100 33 13 4.7 0[2]
[1] [2]
RADS[1] (k)
R/W Parallel mode 13 78h 76h 74h 72h 70h 33 58h 56h 54h 52h 50h 100 68h 66h 64h 62h 60h open 78h 76h 74h 72h 70h 1 = Read from TDF8599B 0 = Write to TDF8599B
4.7 68h 66h 64h 62h 60h
58h 56h 54h 52h 50h
non-I2C-bus
mode select
Required external resistor accuracy is 1 %. Short circuited to ground.
In I2C-bus mode, pins MOD and ADS can be latched using the I2C-bus command IB3[D7] = 1. This avoids disturbances from amplifier outputs of other TDF8599B devices in the same application switching and generating incorrect information on the MOD and ADS pins.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
In non-I2C mode or when IB3[D7] = 0, the information on the MOD and ADS pins is latched when one of the TDF8599B's outputs starts switching.
SCL
SCL
SDA
SDA
Mp SLAVE
START
(1)
STOP
Mp SLAVE
(1) (2)
001aai792
001aai793
(1) When SCL is HIGH, SDA changes to form the start or stop condition.
(1) SDA is allowed to change. (2) All data bits must be valid on the positive edges of SCL.
Fig 22.
I2C-bus
start and stop conditions
Fig 23. Data bits sent from Master microprocessor (Mp)
SCL
1
2
7
8
9
1
2
7
8
9
SDA
MSB
MSB - 1
LSB + 1
ACK
MSB
MSB - 1
LSB + 1
LSB
ACK
Mp START SLAVE
ADDRESS
WRITE ACK
WRITE DATA ACK(1)
STOP
001aai794
(1) To stop the transfer after the last acknowledge a stop condition must be generated.
Fig 24. I2C-bus write
SCL
1
2
7
8
9
1
2
7
8
9
SDA
MSB
MSB - 1
LSB + 1
ACK
MSB
MSB - 1
LSB + 1
LSB
Mp SLAVE
START
ADDRESS
READ ACKNOWLEDGE READ DATA
ACK(1)
STOP
001aai795
(1) To stop the transfer, the last byte must not be acknowledged (SDA is HIGH) and a stop condition must be generated.
Fig 25. I2C-bus read
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
9.1 Instruction bytes
If R/W bit = 0, the TDF8599B expects three instruction bytes: IB1, IB2 and IB3. After a power-on reset, all unspecified instruction bits must be set to zero.
Table 14. Bit D7 Instruction byte descriptions Description Instruction byte IB1 0 offset detection on pin DIAG Instruction byte IB2 offset protection on Instruction byte IB3 latch information on pins ADS and MOD when the amplifier starts switching latch information on pins ADS and MOD; see Section 9 on page 23 disable AC load detection enable AC load detection oscillator phase shift bits IB3[D3] to IB3[D1][2]
Value
1
no offset detection on pin DIAG
offset protection off
D6 D5 D4 D3
0 1 0 1 0 1 0 1
channel 1 offset monitoring on channel 1 offset monitoring off channel 1 clip detect on pin CLIP channel 1 no clip detect on pin CLIP disable frequency hopping enable frequency hopping[1] oscillator frequency as set with Rosc - 10 % oscillator frequency as set with Rosc + 10 % channel 1 enabled channel 1 disabled TDF8599B in Standby mode TDF8599B in Mute or Operating modes[3]
channel 2 offset monitoring on channel 2 offset monitoring off channel 2 clip detect on pin CLIP channel 2 no clip detect on pin CLIP thermal pre-warning on pin CLIP no thermal pre warning on pin CLIP temperature pre-warning at 140 C temperature pre-warning at 120 C DC-load detection disabled DC-load detection enabled channel 2 enabled channel 2 disabled all channels operating all channels muted
D2 D1 D0
0 1 0 1 0 1
AD modulation BD modulation
[1] [2] [3]
See Section 8.3.3 on page 9 for information on IB1[D4] and IB[D3]. See Table 15 "Phase shift bit settings" for information on IB3[D3] to IB3[D1]. See Table 4 for information on IB1[D0] and IB2[D0].
Table 15. D3 0 0 0 0 1 1
Phase shift bit settings D2 0 0 1 1 0 0 D1 0 1 0 1 0 1 Phase 0
1 4 1 3 1 2 2 3 3 4

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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
9.2 Data bytes
If R/W = 1, the TDF8599B sends two data bytes to the microprocessor (DB1 and DB2). All short diagnostic and offset protection bits are latched. In addition, all bits are reset after a read operation except the DC load detection bits (DBx[D4], DB1[D6]). The default setting for all bits is logic 0. In Parallel mode, the diagnostic information is stored in byte DB1.
Table 16. Bit D7 0 1 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description of data bytes DB1 channel 1 at least 1 instruction bit set to logic 1 all instruction bits are set to logic 0 invalid DC load data valid DC load data no overvoltage overvoltage protection active speaker load channel 1 open load channel 1 no shorted load channel 1 shorted load channel 1 no offset offset detected no short to VP channel 1 short to VP channel 1 no short to ground channel 1 short to ground channel 1 DB2 channel 2 below maximum temperature maximum temperature protection activated no temperature warning temperature pre-warning active no undervoltage undervoltage protection active speaker load channel 2 open load channel 2 no shorted load channel 2 shorted load channel 2 reserved reserved no short to VP channel 2 short to VP channel 2 no short to ground channel 2 short to ground channel 2
Value
Data byte DB1[D7] indicates whether the instruction bits have been set to logic 0. In principle, DB1[D7] is set after a POR or when all the instruction bits are programmed to logic 0. Pin DIAG is driven HIGH when bit DB1[D7] = 1.
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I2C-bus controlled dual channel class-D power amplifier
10. Limiting values
Table 17. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP Parameter supply voltage Conditions Operating mode off state load dump; duration 50 ms; tr > 2.5 ms IORM IOM repetitive peak output current peak output current maximum output current limiting maximum; non-repetitive stereo mode parallel mode Vi input voltage pins SCL, SDA, ADS, MOD, SSM, OSCIO, EN and SEL_MUTE pins IN1N, IN1P, IN2N and IN2P Vo RESR Tj Tstg Tamb VESD output voltage equivalent series resistance junction temperature storage temperature ambient temperature electrostatic discharge voltage HBM C = 100 pF; Rs = 1.5 k CDM non-corner pins corner pins V(prot) protection voltage AC and DC short circuit voltage of output pins across load and to supply and ground
[5] [4] [3] [2] [1]
Min -1 8
Max 29 +50 50 -
Unit V V V A
0
20 13 5.5
A A V
0 0 -55 -40 -
10 10 350 150 +150 +85 2000
V V m C C C V
pins DIAG and CLIP as seen between pins VP and PGNDn
0
500 750 VP
V V V
[1] [2] [3] [4] [5]
Floating condition assumed for outputs. Current limiting concept. Human Body Model (HBM). Charged-Device Model (CDM). The output pins are defined as the output pins of the filter connected between the TDF8599B output pins and the load.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
11. Thermal characteristics
Table 18. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions in free air Typ 35 1 Unit K/W K/W
12. Static characteristics
Table 19. Static characteristics VP = VDDA = 14.4 V; fosc = 320 kHz; -40 C < Tamb < +85 C; unless otherwise specified. Symbol Supply VP IP Iq(tot) supply voltage supply current total quiescent current off state; Tj 85 C; VP = 14.4 V Operating mode; no load, snubbers and filter connected power switch; Tj = 25 C Tj = 100 C I2C-bus interface: pins SCL and SDA VIL VIH VOL Vi Ii Vi LOW-level input voltage HIGH-level input voltage LOW-level output voltage input voltage input current input voltage pin SDA; Iload = 5 mA pins not connected pins shorted to GND pin EN; off state pin EN; Standby mode; mode I2C-bus
[1] [1]
Parameter
Conditions
Min 8 -
Typ 14.4 2 90
Max 24 10 120
Unit V A mA
Series resistance output switches RDSon drain-source on-state resistance 0 2.3 0 1.5 80 0 2 2 0 3 140 190 2 105 150 205 1.5 5.5 0.4 2.7 160 0.8 5 5 0.8 5 5 50 m m V V V V A V V V V V A A
Address, phase shift and modulation mode select: pins ADS and MOD
Enable and SEL_MUTE input: pins EN and SEL_MUTE
pin EN; Mute mode or Operating mode; non-I2C-bus mode pin SEL_MUTE; Mute mode; voltage on pin EN > 2 V pin SEL_MUTE; Operating mode; voltage on pin EN > 2 V Ii input current pin EN; 2.5 V pin SEL_MUTE; Operating mode; 0.8 V
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Table 19. Static characteristics ...continued VP = VDDA = 14.4 V; fosc = 320 kHz; -40 C < Tamb < +85 C; unless otherwise specified. Symbol Diagnostic output THDclip Vth(offset) VOL IL total harmonic distortion clip detection level threshold voltage for offset detection LOW-level output voltage leakage current DIAG or CLIP pins activated; Io = 1 mA DIAG and CLIP pins; diagnostic not activated
[2][3]
Parameter
Conditions
Min 1 -
Typ 0.2 2 -
Max 3 0.3 50
Unit % V V A
Audio inputs; pins IN1N, IN1P, IN2N and IN2P Vi Vref input voltage reference voltage input ACGND pin half supply reference SVRR pin Amplifier outputs; pins OUT1N, OUT1P, OUT2N and OUT2P VO(offset) output offset voltage BTL; Mute mode BTL; Operating mode Stabilizer output; pins VSTAB1 and VSTAB2 Vo output voltage stabilizer output in Mute mode and Operating mode undervoltage; amplifier is muted overvoltage; load dump protection is activated VP that a POR occurs at Current protection IO(ocp) overcurrent protection output current protection temperature thermal foldback activation temperature average junction temperature for pre-warning 1 average junction temperature for pre-warning 2 load detection threshold impedance open load detection threshold impedance AC load detection output threshold current
Rev. 01 -- 29 July 2009
[4][6]
2 6.9 8
2.45 2.45 7.2 10
3 7.5 25 70 12
V V V mV mV V
SVRR voltage and ACGND input bias voltage in Mute and Operating modes
Voltage protections V(prot) protection voltage 6.8 26.2 3 8 7.2 27 3.7 9.5 8 4.6 11 V V V A
current limiting concept
Temperature protection Tprot Tact(th_fold) Tj(AV)(warn1) Tj(AV)(warn2) 155 gain = -1 dB IB2[D3] = 0; non-I2C-bus mode IB2[D3] = 1 140 140 120 160 150 150 130 C C C C
DC load detection levels: I2C-bus mode only[7] Zth(load) Zth(open) for normal speaker load; DB1[D4] = 0; DB2[D4] = 0 DB1[D4] = 1; DB2[D4] = 1 350 25
AC load detection levels: I2C-bus mode only Ith(o)det(load)AC
TDF8599B_1
250
500
700
mA
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Table 19. Static characteristics ...continued VP = VDDA = 14.4 V; fosc = 320 kHz; -40 C < Tamb < +85 C; unless otherwise specified. Symbol twake tdet(DCload) td(stb-mute) Parameter wake-up time DC load detection time delay time from standby to mute Conditions on pin EN before first I2C-bus transmission is recognized CON = 470 nF measured from amplifier enabling to start of unmute (no DC load detection); CSVRR = 47 F CON = 470 nF CON = 470 nF shutdown delay time from EN pin LOW to SVRR LOW; voltage on pin SVRR < 0.1 V; CSVRR = 47 F shutdown delay time from EN pin LOW to SVRR LOW; voltage on pin SVRR < 0.1 V; CSVRR = 47 F; VP = 35 V shutdown hold delay time from pin EN LOW to ACGND LOW; voltage on pin ACGND < 0.1 V; Master mode hold delay in Master mode to allow slaved devices to shutdown fosc = 320 kHz Speaker load impedance RL load resistance at supply voltage equal to or below 24 V stereo mode parallel mode
[1] [2] [3] [4] [5] [6] [7] Required resistor accuracy for pins ADS and MOD is 1 %; see Section 9 on page 23. Maximum leakage current from DCP pin to ground = 3 A. The output offset values can be either positive or negative. The Vth(offset) limit values (excluding Typ) are the valid absolute values. DC output offset voltage is applied to the output gradually during the transition between Mute mode and Operating mode. I2C-bus mode only. The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin. The DC load valid bit DB1[D6] must be used; Section 8.6.2.1 on page 18. The DC load enable bit IB2[D2] must be reset after each load detection cycle to prevent amplifier hang-up incidents.
[6] [5]
Min -
Typ 380 140
Max 500 -
Unit s ms ms
Start-up/shut-down/mute timing
[5]
td(mute-fgain) td
mute to full gain delay time delay time
200
15 350
550
ms ms
300
400
700
ms
-
370
-
ms
-
50
-
ms
1.6 0.8
4 -
-

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I2C-bus controlled dual channel class-D power amplifier
12.1 Switching characteristics
Table 20. Switching characteristics VP = VDDA = 14.4 V; -40 C < Tamb < +85 C; unless otherwise specified. Symbol fosc Parameter oscillator frequency Conditions external clock frequency; Rosc = 39 k internal fixed frequency and Spread spectrum mode frequency based on the resistor value connected to pin OSCSET for the master setting Master/slave setting (OSCIO pin) Rosc VOL VOH VIL VIH ftrack Nslave fosc oscillator resistance LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage tracking frequency number of slaves oscillator frequency variation resistor value on pin OSCSET; master setting output output input input PLL enabled driven by one master between maximum and minimum values; Spread spectrum mode activated Spread spectrum mode activated; CSSM = 1 F change positive; IB1[D4] = 1; IB1[D3] = 1 change negative; IB1[D4] = 1; IB1[D3] = 0 Timing tr tf tw(min) rise time fall time minimum pulse width PWM output; Io = 0 A PWM output; Io = 0 A Io = 0 A 10 10 80 ns ns ns 26 4 4 300 12 39 10 49 0.8 0.8 500 % k V V V V kHz Min 300 Typ 320 Max 450 Unit kHz kHz Internal oscillator
Spread spectrum mode setting
fsw
switching frequency
-
7
-
Hz
Frequency hopping fosc(int) internal oscillator frequency fosc + 10 % fosc - 10 % kHz kHz
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I2C-bus controlled dual channel class-D power amplifier
13. Dynamic characteristics
Table 21. Dynamic characteristics VP = VDDA = 14.4 V; RL = 4 ; fi = 1 kHz; fosc = 320 kHz; Rs(L) < 0.04 [1]; -40 C < Tamb < +85 C; Stereo mode; unless otherwise specified. Symbol Po Parameter output power Conditions Stereo mode: VP = 14.4 V; THD = 1 %; RL = 4 VP = 14.4 V; THD = 10 %; RL = 4 square wave (EIAJ); RL = 4 VP = 24 V; THD = 10 %; RL = 4 VP = 14.4 V; THD = 1 %; RL = 2 VP = 14.4 V; THD = 10 %; RL = 2 square wave (EIAJ); RL = 2 Parallel mode: VP = 14.4 V; THD = 10 %; RL = 1 VP = 24 V; THD = 10 %; RL = 2 VP = 24 V; THD = 1 %; RL = 1 THD Gv(cl) cs SVRR total harmonic distortion closed-loop voltage gain channel separation supply voltage rejection ratio fi = 1 kHz; Po = 1 W Operating mode fripple = 100 Hz fripple = 1 kHz Mute mode fripple = 1 kHz off state and Standby mode fripple = 1 kHz |Zi(dif)| Vn(o) differential input impedance output noise voltage Operating mode BD mode AD mode Mute mode BD mode AD mode bal(ch) mute CMRR po
[1]
[6] [6] [5] [5] [4] [4] [4] [4] [2] [2]
Min 18 24 29 39 135
[3] [3]
Typ 20 26 40 70 32 43 70 85 138 150 0.02 0.02 26 70 70 70 70 90 100 60 100 25 85 0 80 90
Max 0.1 0.1 27 150 77 140 32 110 1 -
Unit W W W W W W W W W W % % dB dB dB dB dB dB k V V V V dB dB dB %
fi = 1 kHz; Po = 1 W fi = 10 kHz; Po = 1 W
25 60 60 60 60 66 65 -
channel balance mute attenuation common mode rejection ratio output power efficiency Vi(cm) = 1 V RMS Po = 20 W
[7]
Rs(L) is the sum of the inductor series resistance from the low-pass LC filter in the application together with all resistance from PCB traces or wiring between the output pin of the TDF8599B and the inductor to the measurement point. LC filter dimensioning is L = 10 H, C = 1 F for 4 load and L = 5 H, C = 2.2 F for 2 load. Output power is measured indirectly based on RDSon measurement.
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[2]
TDF8599B_1
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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
[3] [4] [5] [6] [7]
Total harmonic distortion is measured at the bandwidth of 22 Hz to 20 kHz, AES brick wall. The maximum limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 . B = 22 Hz to 20 kHz, AES brick wall, Rs = 0 . B = 22 Hz to 20 kHz, AES brick wall, independent of Rs. Vi = Vi(max) = 0.5 V RMS.
14. Application information
14.1 Output power estimation (Stereo mode)
The output power, just before clipping, can be estimated using Equation 5:
2 RL f osc ----------------------------------------------------- x 1 - t - w ( min ) x --------- x V P R L + 2 x ( R DSon + R s ) 2 P o = --------------------------------------------------------------------------------------------------------------------------------------- [ W ] 2 x RL
(5)
Where,
* * * * * *
VP = supply voltage (V) RL = load impedance () RDSon = drain-source on-state resistance () Rs = series resistance of the output inductor () tw(min) = minimum pulse width(s) depending on output current (s) fosc = oscillator frequency in Hz (typically 320 kHz)
The output power at 10 % THD can be estimated by: P o ( 2 ) = 1.25 x P o ( 1 ) where Po(1) = 0.5 % and Po(2) = 10 %. Figure 26 and Figure 27 show the estimated output power at THD = 0.5 % and THD = 10 % as a function of supply voltage for different load impedances in stereo mode.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Po (W)
70 60 50 40
001aak225
80 Po (W) 60
(1)
001aak226
(1)
40 30 20 10 0 8 12 16 20 VP (V) 24 0 8 12 16
(2)
(2)
20
20 VP (V)
24
THD = 0.5 %. RDSon = 0.19 (at Tj = 100 C), Rs = 0.05 , tw(min) = 190 ns and IO(ocp) = 8 A (minimum). (1) RL = 2 . (2) RL = 4 .
THD = 10 %. RDSon = 0.19 (at Tj = 100 C), Rs = 0.05 , tw(min) = 190 ns and IO(ocp) = 8 A (minimum). (1) RL = 2 . (2) RL = 4 .
Fig 26. Po as a function of VP in stereo mode with THD = 0.5 %
Fig 27. Po as a function of VP in stereo mode with THD = 10 %
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
14.2 Output power estimation (Parallel mode)
Figure 28 and Figure 29 show the estimated output power at THD = 0.5 % and THD = 10 % as a function of the supply voltage for different load impedances in parallel mode.
150 Po (W) 120
001aak227
180 Po (W) 150
001aak228
120 90
(1) (1)
90 60
(2)
60
(2)
30
(3)
(3)
30
0 8 12 16 20 VP (V) 24
0 8 12 16 20 VP (V) 24
THD = 0.5 %. RDSon = 0.1 (at Tj = 100 C), Rs = 0.025 , tw(min) = 190 ns and IO(ocp) = 16 A (minimum). (1) RL = 1 . (2) RL = 2 . (3) RL = 4 .
THD = 10 %. RDSon = 0.1 (at Tj = 100 C), Rs = 0.025 , tw(min) = 190 ns and IO(ocp) = 16 A (minimum). (1) RL = 1 . (2) RL = 2 . (3) RL = 4 .
Fig 28. Po as a function of VP in parallel mode with THD = 0.5 %
Fig 29. Po as a function of VP parallel mode with THD = 10 %
14.3 Output current limiting
The peak output current is internally limited to 8 A maximum. During normal operation, the output current should not exceed this threshold level otherwise the output signal will be distorted. The peak output current can be estimated using Equation 6: VP I o ----------------------------------------------------- 8 [ A ] R L + 2 x ( R DSon + R s ) (6)
* * * * *
Io = output current (A) VP = supply voltage (V) RL = load impedance () RDSon = on-resistance of power switch () Rs = series resistance of output inductor ()
Example: A 2 speaker can be used with a supply voltage of 19 V before current limiting is triggered. Current limiting (clipping) avoids audio holes but can cause distortion similar to voltage clipping. In Parallel mode, the output current is internally limited above 16 A.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
14.4 Speaker configuration and impedance
A flat-frequency response (due to a 2nd order Butterworth filter) is obtained by changing the low-pass filter components (LLC, CLC) based on the speaker configuration and impedance. Table 22 shows the required values.
Table 22. 1 2 4 Filter component values LLC (H) 2.5 5 10 CLC (F) 4.4 2.2 1
Load impedance ()
Remark: When using a 1 load impedance in Parallel mode, the outputs are shorted after the low-pass filter switches two 2 filters in parallel.
14.5 Heat sink requirements
In most applications, it is necessary to connect an external heat sink to the TDF8599B. Thermal foldback activates at Tj = 140 C. The expression below shows the relationship between the maximum power dissipation before activation of thermal foldback and the total thermal resistance from junction to ambient: T j ( max ) - T amb R th ( j-a ) = ----------------------------------- [ K W ] P max (7)
Pmax is determined by the efficiency () of the TDF8599B. The efficiency measured as a function of output power is given in Figure 43. The power dissipation can be derived as a function of output power (see Figure 42). Example 1:
* * * * * *
VP = 14.4 V Po = 2 x 25 W into 4 (THD = 10 % continuous) Tj(max) = 140 C Tamb = 25 C Pmax = 5.8 W (from Figure 42) The required Rth(j-a) = 115 C / 5.8 W = 19 K/W
The total thermal resistance Rth(j-a) consists of: Rth(j-c) + Rth(c-h) + Rth(h-a) Where:
* Thermal resistance from junction to case (Rth(j-c)) = 1 K/W * Thermal resistance from case to heat sink (Rth(c-h)) = 0.5 K/W to 1 K/W (depending on
mounting)
* Thermal resistance from heat sink to ambient (Rth(h-a)) would then be
19 - (1 + 1) = 17 K/W. If an audio signal has a crest factor of 10 (the ratio between peak power and average power = 10 dB) then Tj will be much lower.
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Example 2:
* * * * * *
VP = 14.4 V Po = 2 x (25 W / 10) = 2 x 2.5 W into 4 (audio with crest factor of 10) Tamb = 25 C Pmax = 2.5 W Rth(j-a) = 19 K/W Tj(max) = 25 C + (2.5 W x 19 K/W) = 72 C
14.6 Curves measured in reference design
102 THD + N (%) 10
001aak229
102 THD + N (%) 10
001aak231
1
1
10-1
(3) (2)
10-1
(3) (2)
10-2
(1)
10-2
(1)
10-3 10-1
1
10 Po (W)
102
10-3 10-1
1
10 Po (W)
102
(1) VP = 14.4 V, RL = 2 at 6 kHz. (2) VP = 14.4 V; RL = 2 at 1 kHz. (3) VP = 14.4 V; RL = 2 at 100 Hz.
(1) VP = 14.4 V, RL = 4 at 6 kHz. (2) VP = 14.4 V; RL = 4 at 1 kHz. (3) VP = 14.4 V; RL = 4 at 100 Hz.
Fig 30. THD + N as a function of output power with a 2 load; VP = 14.4 V
Fig 31. THD + N as a function of output power with a 4 load; VP = 14.4 V
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
102 THD + N (%) 10
001aak232
102 THD + N (%) 10
001aak233
1
(3)
1
(3)
10-1
(2)
10-1
(2)
10-2
(1)
10-2
(1)
10-3 10-1
1
10
102 Po (W)
103
10-3 10-1
1
10 Po (W)
102
(1) VP = 24 V, RL = 2 at 6 kHz. (2) VP = 24 V; RL = 2 at 1 kHz. (3) VP = 24 V; RL = 2 at 100 Hz.
(1) VP = 24 V, RL = 4 at 6 kHz. (2) VP = 24 V; RL = 4 at 1 kHz. (3) VP = 24 V; RL = 4 at 100 Hz.
Fig 32. THD + N as a function of output power with a 2 load; VP = 24 V
1 THD + N (%) 10-1
001aak238
Fig 33. THD + N as a function of output power with a 4 load; VP = 24 V
1 THD + N (%) 10-1
001aak239
(1)
10-2
(2)
10-2
(1) (2)
10-3 10
102
103
104 f (Hz)
105
10-3 10
102
103
104 f (Hz)
105
(1) VP = 14.4 V; RL = 2 at 1 W. (2) VP = 14.4 V; RL = 2 at 10 W.
(1) VP = 14.4 V; RL = 4 at 1 W. (2) VP = 14.4 V; RL = 4 at 10 W.
Fig 34. THD + N as a function of frequency with a 2 load, BD modulation; VP = 14.4 V
Fig 35. THD + N as a function of frequency with a 4 load, BD modulation; VP = 14.4 V
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
1 THD + N (%) 10-1
001aak241
30 G (dB) 28
001aak240
26
24 10-2
(1) (2)
22
10-3 10
102
103
104 f (Hz)
105
20 10
102
103
104 f (Hz)
105
(1) VP = 24 V; RL = 2 at 1 W. (2) VP = 24 V; RL = 2 at 10 W.
Fig 36. THD + N as a function of frequency with a 2 load, BD modulation; VP = 24 V
120 Po (W)
(2) (3)
Fig 37. Gain as a function of frequency
001aak243
(1)
80 Po (W) 60
001aak242
(1)
(2) (3)
80
40
40 20
0 10 14 18 22 VP (V) 26
0 10 14 18 22 VP (V) 26
f = 1 kHz; RL = 2 . (1) THD = 10 %. (2) THD = 3 %. (3) THD = 1 %.
f = 1 kHz; RL = 4 . (1) THD = 10 %. (2) THD = 3 %. (3) THD = 1 %.
Fig 38. Output power as a function of supply voltage with a 2 load
Fig 39. Output power as a function of supply voltage with a 4 load
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Product data sheet
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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
-60 cs (dB) -70
001aak244
-50 cs (dB) -60
001aak245
-70 -80 -80 -90
-90
-100 10
102
103
104 f (Hz)
105
-100 10
102
103
104 f (Hz)
105
VP = 14.4 V; RL = 4 at 1 W.
VP = 14.4 V; RL = 4 at 10 W.
Fig 40. Channel separation as a function of frequency with 1 W output power, BD modulation
25 PD (W) 20
(1)
Fig 41. Channel separation as a function of frequency with 10 W output power, BD modulation
100 (%) 80
(1) (2)
001aak246
001aak247
15
60
10
(2)
40
5
20
0 0 20 40 Po (W) 60
0 0 20 40 Po (W) 60
VP = 14.4 V. (1) RL = 2 . (2) RL = 4 .
VP = 24 V. (1) RL = 4 . (2) RL = 2 .
Fig 42. Power dissipation as a function of total output power with both channels driven; VP = 14.4 V
Fig 43. Efficiency as a function of total output power with both channels driven; VP = 24 V
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
60 PD (W) 40
001aak248
(1)
100 (%) 80
(1)
001aak249
(2)
60
40 20
(2)
20
0 0 40 80 Po (W) 120
0 0 40 80 Po (W) 120
VP = 24 V. (1) RL = 2 . (2) RL = 4 .
VP = 24 V. (1) RL = 4 . (2) RL = 2 .
Fig 44. Power dissipation as a function of total output power with both channels driven; VP = 24 V
Fig 45. Efficiency as a function of total output power with both channels driven; VP = 24 V
-70 CMRR (dB) -74
001aak250
-78
-82
-86
-90 10
102
103
104 f (Hz)
105
VP = 14.4 V; Vi = 1 V RMS.
Fig 46. CMRR as a function of frequency
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
14.7 Typical application schematics
bead bead bead VP GND PGND2 GNDD/HW
100 nF 220 nF LLC 1000 F 35 V 100 F 35 V 100 F 35 V
VP1 VP2
VPA PGND1
36 35 34 33 32 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
IN1P CIN1P IN1N CIN1N IN2P
CIN2P
470 nF 470 nF 470 nF 470 nF
IN1P IN1N IN2P IN2N
VDDD VSTAB1 OUT1N
OUT1N
100 nF 22 470 pF 470 pF CLC 10 15 nF
IN2N CIN2N ACGND EN
BOOT1N VP1
CACGND 100 nF
VP1
100 nF
enable(1) mute/on(1)
470 nF 47 F 2.2 F
VP1
22 100 nF 470 pF CLC LLC LLC
PGND1
470 pF 10
PGND1 30 PGND1 BOOT1P 29 OUT1P OUT2P 28 27 26 25 24 23 22 21 20 19
SEL_MUTE SVRR AGND VDDA ADS MOD CLIP DIAG SDA SCL SSM OSCSET
1 F(2) 100 nF 39 k 4.7 k 10 k
15 nF
OUT1P OUT2P
100 nF 22
TDF8599B
CLC
10
15 nF
bead
VPA non-I2C-bus mode BD modulation setting VPull-up
BOOT2P
470 pF
470 pF 470 pF 10
PGND2 PGND2
100 nF
VP2
22 100 nF 470 pF CLC LLC
PGND2 VP2
VP2 BOOT2N
10 k
VPull-up
15 nF 220 nF
OUT2N
OUT2N VSTAB2 DCP OSCIO
(3)
MASTER MODE
001aak220
Dual BTL mode (stereo) in non-I2C-bus mode with DC offset protection disabled; Spread spectrum mode enabled BD modulation. (1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE. (2) See Section 8.3.2 on page 8 for detailed information. (3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 47. Example application diagram for dual BTL in non-I2C-bus mode
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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
bead bead bead VP GND PGND2 GNDD/HW
100 nF 220 nF LLC 1000 F 35 V 100 F 35 V 100 F 35 V
VP1 VP2
VPA PGND1
36 35 34 33 32 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
IN1P CIN1P IN1N CIN1N IN2P CIN2P IN2N CIN2N ACGND EN
470 nF 470 nF 470 nF 470 nF
IN1P IN1N IN2P IN2N
VDDD VSTAB1 OUT1N
OUT1N
100 nF 22 470 pF 470 pF CLC 10 15 nF
BOOT1N VP1
CACGND 100 nF
VP1
100 nF
enable(1)
VP1
22 100 nF 470 pF CLC LLC LLC
PGND1
470 pF 10
PGND1 30 PGND1 BOOT1P 29 OUT1P OUT2P 28
SEL_MUTE(1) SVRR AGND VDDA ADS MOD CLIP DIAG SDA SCL SSM OSCSET
100 nF 39 k 2.2 F 470 nF 47 F
15 nF
OUT1P OUT2P
100 nF 22
TDF8599B
27 26 25 24 23 22 21 20 19
CLC
10
15 nF
bead
RADS 13 k 10 k
VPA I2C-bus address select stereo mode setting VPull-up
BOOT2P
470 pF
470 pF 470 pF 10
PGND2 PGND2
100 nF
VP2
22 100 nF 470 pF CLC LLC
PGND2
VP2 VP2 BOOT2N
10 k
VPull-up connect to P
(2)
15 nF 220 nF
OUT2N
OUT2N VSTAB2 DCP
(3)
4.7 F
OSCIO
MASTER MODE
001aak221
Dual BTL mode (stereo) in I2C-bus mode with DC offset protection enabled; Spread spectrum mode disabled. (1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE. (2) See Section 8.3.2 on page 8 for detailed information. (3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 48. Example application diagram for dual BTL in I2C-bus mode
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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
bead bead bead VP GND PGND2 GNDD/HW
100 nF 220 nF LLC 10 15 nF 1000 F 35 V 100 F 35 V 100 F 35 V
VP1 VP2
VPA PGND1
36 35 34 33 32 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
IN1P IN1N IN2P IN2N ACGND EN
CINP CINN
470 nF 470 nF
INP INN
VDDD VSTAB1 OUT1N BOOT1N VP1
CACGND 100 nF
470 pF
470 pF
VP1
100 nF
enable(1)
OUTN
100 nF CLC
VP1
470 pF
PGND1
470 pF 10
PGND1 30 PGND1 BOOT1P 29 OUT1P OUT2P 28
SEL_MUTE(1) SVRR AGND VDDA ADS MOD CLIP DIAG SDA SCL SSM OSCSET
100 nF 39 k 2.2 F 470 nF 47 F
22
LLC LLC
15 nF
TDF8599B
27 26 25 24 23 22 21 20 19
22 CLC 470 pF
10
15 nF
bead
RADS 33 k 10 k
VPA I2C-bus address select parallel mode setting VPull-up
BOOT2P
100 nF
470 pF 470 pF 10
PGND2 PGND2
100 nF
OUTP
VP2
470 pF
PGND2
VP2
VP2 BOOT2N
10 k
VPull-up connect to P fixed frequency(2) MASTER MODE
001aak222
LLC
15 nF 220 nF
OUT2N VSTAB2 DCP
(3)
4.7 F
OSCIO
Single BTL mode (parallel) in I2C-bus mode with DC offset protection enabled; Spread spectrum mode disabled. (1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE. (2) See Section 8.3.2 on page 8 for detailed information. (3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 49. Example application diagram for a single BTL in I2C-bus mode
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Product data sheet
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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
bead bead bead VP GND
1000 F 35 V 100 F 35 V 100 F 35 V
VP1 VP2 GNDD/HW
100 nF 220 nF
VPA PGND1 PGND2
LLC
36 35 34 33 32 31 30 29 28
1 2 3 4 5 6 7 8 9
IN1P CIN1P IN1N CIN1N IN2P CIN2P IN2N CIN2N ACGND EN(1)
470 nF 470 nF 470 nF 470 nF
IN1P IN1N IN2P IN2N
VDDD VSTAB1 OUT1N
OUT1N
100 nF 22 470 pF 470 pF CLC 10 15 nF
BOOT1N VP1 PGND1
CACGND 100 nF
VP1
100 nF
enable
VP1
22 100 nF 470 pF CLC LLC LLC
PGND1
470 pF 10
SEL_MUTE(1) SVRR AGND VDDA ADS MOD CLIP DIAG SDA SCL SSM OSCSET
1 F 100 nF 39 k 2.2 F 470 nF 47 F
PGND1 BOOT1P OUT1P OUT2P
15 nF
OUT1P OUT2P
100 nF 22
TDF8599B
27 MASTER 10 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
CLC
10
15 nF
bead
RADS 13 k 10 k
VPA I2C-bus address select stereo mode setting VPull-up
BOOT2P
470 pF
470 pF 470 pF 10
PGND2 PGND2
100 nF
VP2
22 100 nF 470 pF CLC LLC
PGND2
VP2
VP2 BOOT2N
10 k
VPull-up
15 nF 220 nF
OUT2N
OUT2N VSTAB2 DCP
DC offset protection enabled
(3) 20 k
4.7 F
OSCIO
spread spectrum mode(2) MASTER MODE
470 nF
GNDD/HW
100 nF 220 nF LLC 10 15 nF
36 35 34 33 32 31
1 2 3 4 5 6 7 8 9
IN1P IN1N IN2P IN2N ACGND EN(1)
CINP CINN
IN3P
470 nF
VDDD VSTAB1 OUT1N BOOT1N VP1
IN3N
CACGND 100 nF
470 pF
470 pF
VP1
100 nF
OUT3N
100 nF CLC
VP1
470 pF
PGND1
470 pF 10
PGND1 30 PGND1 BOOT1P 29 OUT1P OUT2P 28
SEL_MUTE(1) SVRR AGND VDDA ADS MOD CLIP DIAG SDA SCL SSM OSCSET
5.1 k 270 nF 2.2 F 470 nF 47 F
22
LLC LLC
15 nF
TDF8599B
27 SLAVE 10 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
22 CLC 470 pF
10
15 nF
bead
RADS 33 k 10 k
VPA I2C-bus address select parallel mode setting VPull-up
BOOT2P
100 nF
470 pF 470 pF 10
PGND2 PGND2
100 nF
OUT3P
VP2
470 pF
PGND2
VP2
VP2 BOOT2N
10 k
VPull-up connect to P phase lock operation
(4)
LLC
15 nF 220 nF
OUT2N VSTAB2 DCP
DC offset protection enabled
(3)
4.7 F
OSCIO
10 nF
SLAVE MODE
001aak223
I2C-bus mode: Dual BTL Master mode, one BTL in Slave mode; DC offset protection enabled. (1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE. (2) See Section 8.3.2 on page 8 for detailed information. (3) See Section 8.5.5 on page 16 for detailed information on DC offset protection. (4) See Section 8.3.4 on page 10 for detailed information on PLL operation.
Fig 50. Master-slave example application diagram; two BTL masters and one BTL slave in I2C-bus mode
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TDF8599B
I2C-bus controlled dual channel class-D power amplifier
15. Package outline
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height SOT851-2
D x
E
A
c y E2 HE X v
M
A
D1 D2 1 18
pin 1 index Q E1 A2 (A 3) A4 Lp detail X 36 z e 19 w A
bp
M
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. A2 mm 3.5 A3 A4(1) bp c D (2) D1 D2 1.1 0.9 E (2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 0.65 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.55 2.20 8 0
+0.08 3.5 0.35 -0.04 3.2
0.38 0.32 16.0 13.0 0.25 0.23 15.8 12.6
0.25 0.12 0.03 0.07
Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT851-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-05-04
Fig 51. Package outline SOT851-2 (HSOP36)
TDF8599B_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 29 July 2009
46 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
16. Handling information
In accordance with SNW-FQ-611-D. The number of the quality specification can be found in the Quality Reference Handbook. The handbook can be ordered using the code 9398 510 63011.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
TDF8599B_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 29 July 2009
47 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 52) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 23 and 24
Table 23. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 24. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 52.
TDF8599B_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 29 July 2009
48 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 52. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Abbreviations
Table 25. BCDMOS BTL DCP DMOST EMI I2C LSB Mp MSB NDMOST OCP OTP OVP POR PWM SOI TFP UVP WP
TDF8599B_1
Abbreviations Description Bipolar Complementary and double Diffused Metal-Oxide Semiconductor Bridge-Tied Load DC offset Protection double Diffused Metal-Oxide Semiconductor Transistor ElectroMagnetic Interference Inter-Integrated Circuit Least Significant Bit Master microprocessor Most Significant Bit N-type double Diffused Metal-Oxide Semiconductor Transistor OverCurrent Protection OverTemperature Protection OverVoltage Protection Power-On Reset Pulse-Width Modulation Silicon On Insulator Thermal Foldback Protection UnderVoltage Protection Window Protection
(c) NXP B.V. 2009. All rights reserved.
Abbreviation
Product data sheet
Rev. 01 -- 29 July 2009
49 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
19. Revision history
Table 26. Revision history Release date 20090729 Data sheet status Product data sheet Change notice Supersedes Document ID TDF8599B_1
TDF8599B_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 29 July 2009
50 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDF8599B_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 29 July 2009
51 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
22. Tables
Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 I2C-bus mode operation . . . . . . . . . . . . . . . . . . .7 Non-I2C-bus mode operation . . . . . . . . . . . . . . .7 Mode setting pin OSCIO . . . . . . . . . . . . . . . . . .7 Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .10 Operation mode selection with the MOD pin . .11 Overview of protection types . . . . . . . . . . . . . .15 Overview of TDF8599B protection circuits and amplifier states . . . . . . . . . . . . . . .17 Table 11. Available data on pins DIAG and CLIP . . . . . .18 Table 12. Interpretation of DC load detection bits . . . . . .20 Table 13. I2C-bus write address selection using Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. pins MOD and ADS . . . . . . . . . . . . . . . . . . . . . 23 Instruction byte descriptions . . . . . . . . . . . . . . 25 Phase shift bit settings . . . . . . . . . . . . . . . . . . 25 Description of data bytes . . . . . . . . . . . . . . . . . 26 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 27 Thermal characteristics . . . . . . . . . . . . . . . . . . 28 Static characteristics . . . . . . . . . . . . . . . . . . . . 28 Switching characteristics . . . . . . . . . . . . . . . . . 31 Dynamic characteristics . . . . . . . . . . . . . . . . . 32 Filter component values . . . . . . . . . . . . . . . . . 36 SnPb eutectic process (from J-STD-020C) . . . 48 Lead-free process (from J-STD-020C) . . . . . . 48 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 50
23. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Heatsink up (top view) pin configuration TDF8599BTH. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Clock frequency as a function of Rosc . . . . . . . . . .8 Master and slave configuration . . . . . . . . . . . . . . .8 Spread spectrum mode . . . . . . . . . . . . . . . . . . . . .9 Spread spectrum operation in Master mode . . . . .9 Phase lock operation . . . . . . . . . . . . . . . . . . . . . .10 AD/BD modulation switching circuit . . . . . . . . . . .12 AD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .12 BD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Master and slave operation with 12 p phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DC offset protection and diagnostic output . . . . .16 Diagnostic output for short circuit conditions . . . .18 DC load detection circuit . . . . . . . . . . . . . . . . . . .19 DC load detection procedure . . . . . . . . . . . . . . . .19 DC load detection limits . . . . . . . . . . . . . . . . . . . .19 Recommended start-up sequence with DC load detection enabled. . . . . . . . . . . . . . . . . . . . . . . . .21 Start-up and shutdown timing in I2C-bus mode with DC load detection . . . . . . . . . . . . . . . .22 Start-up and shutdown timing in non-I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 I2C-bus start and stop conditions. . . . . . . . . . . . .24 Data bits sent from Master microprocessor (Mmp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 I2C-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Fig 25. I2C-bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fig 26. Po as a function of VP in stereo mode with THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Fig 27. Po as a function of VP in stereo mode with THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Fig 28. Po as a function of VP in parallel mode with THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Fig 29. Po as a function of VP parallel mode with THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Fig 30. THD + N as a function of output power with a 2 W load; VP = 14.4 V. . . . . . . . . . . . . . . . . . . . 37 Fig 31. THD + N as a function of output power with a 4 W load; VP = 14.4 V. . . . . . . . . . . . . . . . . . . . 37 Fig 32. THD + N as a function of output power with a 2 W load; VP = 24 V . . . . . . . . . . . . . . . . . . . . . 38 Fig 33. THD + N as a function of output power with a 4 W load; VP = 24 V . . . . . . . . . . . . . . . . . . . . . 38 Fig 34. THD + N as a function of frequency with a 2 W load, BD modulation; VP = 14.4 V . . . . . . . . 38 Fig 35. THD + N as a function of frequency with a 4 W load, BD modulation; VP = 14.4 V . . . . . . . . 38 Fig 36. THD + N as a function of frequency with a 2 W load, BD modulation; VP = 24 V . . . . . . . . . . 39 Fig 37. Gain as a function of frequency. . . . . . . . . . . . . . 39 Fig 38. Output power as a function of supply voltage with a 2 W load . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Fig 39. Output power as a function of supply voltage with a 4 W load . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Fig 40. Channel separation as a function of frequency with 1 W output power, BD modulation . . . . . . . . 40
continued >>
TDF8599B_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 29 July 2009
52 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
Fig 41. Channel separation as a function of frequency with 10 W output power, BD modulation . . . . . . .40 Fig 42. Power dissipation as a function of total output power with both channels driven; VP = 14.4 V . . .40 Fig 43. Efficiency as a function of total output power with both channels driven; VP = 24 V. . . . . . . . . .40 Fig 44. Power dissipation as a function of total output power with both channels driven; VP = 24 V . . . .41 Fig 45. Efficiency as a function of total output power with both channels driven; VP = 24 V. . . . . . . . . .41 Fig 46. CMRR as a function of frequency . . . . . . . . . . . .41 Fig 47. Example application diagram for dual BTL in non-I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . .42 Fig 48. Example application diagram for dual BTL in I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Fig 49. Example application diagram for a single BTL in I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . .44 Fig 50. Master-slave example application diagram; two BTL masters and one BTL slave in I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Fig 51. Package outline SOT851-2 (HSOP36). . . . . . . . .46 Fig 52. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
TDF8599B_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 29 July 2009
53 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
24. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.4 8.4.1 8.4.2 8.4.3 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.6 8.6.1 8.6.2 8.6.2.1 8.6.2.2 8.6.2.3 8.6.2.4 8.6.3 9 9.1 9.2 10 11 12 12.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pulse-width modulation frequency . . . . . . . . . . 7 Master and slave mode selection . . . . . . . . . . . 7 Spread spectrum mode (Master mode) . . . . . . 8 Frequency hopping (Master mode). . . . . . . . . . 9 Phase lock operation (Slave mode) . . . . . . . . 10 Operation mode selection. . . . . . . . . . . . . . . . 11 Modulation mode . . . . . . . . . . . . . . . . . . . . . . 11 Phase staggering (Slave mode) . . . . . . . . . . . 13 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal foldback . . . . . . . . . . . . . . . . . . . . . . 15 Overtemperature protection . . . . . . . . . . . . . . 15 Overcurrent protection . . . . . . . . . . . . . . . . . . 15 Window protection . . . . . . . . . . . . . . . . . . . . . 15 DC offset protection . . . . . . . . . . . . . . . . . . . . 16 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . 17 Overview of protection circuits and amplifier states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . 17 Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 17 Load identification (I2C-bus mode only) . . . . . 18 DC load detection . . . . . . . . . . . . . . . . . . . . . . 18 Recommended start-up sequence with DC load detection enabled . . . . . . . . . . . . . . . . . . . . . . 20 AC load detection . . . . . . . . . . . . . . . . . . . . . . 21 CLIP detection . . . . . . . . . . . . . . . . . . . . . . . . 21 Start-up and shutdown sequence. . . . . . . . . . 22 I2C-bus specification . . . . . . . . . . . . . . . . . . . . 23 Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 25 Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 Thermal characteristics. . . . . . . . . . . . . . . . . . 28 Static characteristics. . . . . . . . . . . . . . . . . . . . 28 Switching characteristics . . . . . . . . . . . . . . . . 31 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 15 16 17 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 23 24 Dynamic characteristics . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Output power estimation (Stereo mode) . . . . Output power estimation (Parallel mode) . . . . Output current limiting . . . . . . . . . . . . . . . . . . Speaker configuration and impedance. . . . . . Heat sink requirements . . . . . . . . . . . . . . . . . Curves measured in reference design . . . . . . Typical application schematics . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 33 33 35 35 36 36 37 42 46 47 47 47 47 47 48 49 50 51 51 51 51 51 51 52 52 54
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 July 2009 Document identifier: TDF8599B_1

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